1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a tri-state output driver configuration.
2. Description of the Related Art
As demand increases for high-speed systems, many of these systems attempt to increase the operating speeds of their memory devices. To increase the operating speed, a semiconductor memory device can minimize a data signal transmission delay in a data path. An example of a data path structure of a semiconductor memory device is disclosed in U.S. Pat. No. 5,966,338.
FIG. 1 is a circuit diagram of a semiconductor memory device that uses a conventional tri-state output driver configuration. Referring to FIG. 1, the semiconductor memory device includes first and second input/output (I/O) line sensing amplifying circuits 11 and 13. The first and second I/O line sensing amplifying circuits 11 and 13 are connected to a data bus line DB, and first and second I/O lines IO1 and IO2, respectively. The first and second I/O lines IO1 and IO2 are connected to a memory cell array (not shown).
When the semiconductor memory device is a double data rate (DDR) synchronous DRAM having an X32 bit organization, there are 32 even-numbered I/O line sensing amplifying circuits and 32 odd-numbered I/O line sensing amplifying circuits are connected to the data bus line DB. For convenience of explanation, FIG. 1 illustrates two I/O line sensing amplifying circuits 11 and 13, the first I/O line sensing amplifying circuit 11 is an even-numbered I/O line sensing amplifying circuit, and the second I/O line sensing amplifying circuit 13 is an odd-numbered I/O line sensing amplifying circuit.
The first I/O line sensing amplifying circuit 11 includes a sensing amplifier 11A that receives and amplifies data received via the first I/O line IO1, and a driver 11B that outputs a tri-state output via the data bus line DB in response to a signal received from the sensing amplifier 11A. The second I/O line sensing amplifying circuit 13 includes a sensing amplifier 13A that receives and amplifies data received via the second I/O line IO2, and a driver 13B that outputs a tri-state output via the data bus line DB in response to a signal received from the sensing amplifier 13A. A signal transmitted via the data bus line DB is output via a multiplexer 15.
The sensing amplifier 11A and the driver 11B of the first I/O line sensing amplifying circuit 11 are arranged together in the same region, and the sensing amplifier 13A and the driver 13B of the second I/O line sensing amplifying circuit 13 are arranged together in a different region. The conventional tri-state output driver configuration described above requires a large data bus line DB, which increases the load on the data bus line DB. The large data bus line DB has a large delay in data transmission that slows the operating speed of the semiconductor memory device.